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Writing testbenches using system verilog \ Janick Begerson

By: Begerson, Janick.
Material type: materialTypeLabelBookPublisher: New Delhi : Springer, 2009Description: xxvi, 412 p.ISBN: 9788184892697.Subject(s): System design | Electronic digital computers--Circuits--Design and construction--Data processingDDC classification: 621.392
Contents:
What is Verification?.- Verification Technologies.- The Verification Plan.- High-Level Modeling.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.- Appendix A: Coding Guidelines.- Appendix B: Glossary.
Summary: Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. This title offers
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Item type Current location Call number Status Date due Barcode Item holds
Books Books Information Technology University, Lahore
621.392 B496W 2009 (Browse shelf) Checked out to Muhammad Umair Shoaib (0001d564a9) 22/03/2024 000279
Total holds: 0

What is Verification?.- Verification Technologies.- The Verification Plan.- High-Level Modeling.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.- Appendix A: Coding Guidelines.- Appendix B: Glossary.

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. This title offers

includes glossary

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